Clock Tree Placement and Routing - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

During the following phases, the Vivado placer determines the placement of MMCM/PLLs, global clock buffers, and the clock root while honoring the physical XDC constraints:

  1. I/O and clock placement

    The placer places I/O buffers and MMCM/PLLs based on connectivity rules and user constraints. The placer assigns clock buffers to clock regions but not to individual sites unless constrained using the LOC property. Only the clock buffers that only drive non-clock loads can move to a different clock region later in the flow based on the placement of their driver and loads.

    Any placer error at this phase is due to conflicting connectivity rules, user constraints, or both. The log file shows extensive information about the possible root cause of the error, which you must review in detail to make the appropriate design or constraint change.

  2. SLR partitioning (SSI technology devices only) and global placement

    The placer performs the initial clock tree implementation based on early driver and load placements. Each clock net is associated with a clock window. The excessive overlap of clock windows can lead to placer errors due to anticipated clock routing contention.

    When a clock partitioning error occurs, the log file shows the last clock budgeting solution for each clock net as well as the number of unique clock nets present in each clock region. Review the log file in detail to determine which clocks to remove from the overutilized clock regions. You can remove clocks using the following methods:

    • Reduce the number of clocks in the design by combining identical synchronous clocks, removing unnecessary MMCM feedback clocks, or consolidating lower fanout clocks with high fanout clocks.
    • Move clock primitives to different clock regions, especially those without connectivity-based placement rules.
    • Add floorplanning constraints on clock loads to keep clocks with smaller fanout closer to their driver or away from the highly utilized clock regions.

    The placer refines the clock tree implementation several times to help improve timing QoR. For example, during the later placement optimization phases, the placer analyzes each challenging clock to determine a better clock root location.

  3. Clock tree pre-routing

    The placer guides the subsequent implementation steps and provides accurate delay estimates for post-place timing analysis.

After placement, the Vivado tools can modify the clock tree implementation as follows:

  • The Vivado physical optimizer can replicate and move cells to clock regions without associated clocks.
  • The Vivado router can make adjustments to improve timing QoR and legalize the clock routing.

The following table summarizes the placement rules for the main clock topologies and how constraints affect these rules.

Table 1. Topologies with and without Placement Rules
Constrained Source Unconstrained Destination Behavior
GCIO BUFGCE, BUFGCTRL, BUFGCE_DIV, PLL/MMCM Automatically placed in same clock region.
PLL/MMCM BUFGCE, BUFGCTRL, BUFGCE_DIV Automatically placed in same clock region.
GT*_CHANNEL BUFG_GT Automatically placed in same clock region.

Automatically placed in same clock region.

Note: You can override placement within same clock region using the CLOCK_REGION constraint.

Unpredictable placement of unconstrained destination BUFG.

Recommend constraining destination BUFG* using the CLOCK_REGION constraint.

Note: This excludes BUFGCTRL > BUFGCTRL.

Unpredictable placement of unconstrained destination MMCM/PLL.

Recommend constraining MMCM/PLL using a LOC constraint.

Recommend CLOCK_DEDICATED_ROUTE constraint when the route spans adjacent or multiple clock regions.