Compile Time Considerations - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

When using the RuntimeOptimized directive with automatic incremental implementation mode or high reuse mode, compile times can be reduced by half if 95% or more of the design is reused. As reuse declines, the benefit to compile time also declines. This is typically predictable unless changes impact critical paths.

When using the TimingClosure directive with automatic incremental implementation mode or high reuse mode, time is spent on running extra algorithms to close timing. Compile time can increase using this mode, especially when it is difficult to close timing or there are timing failures in a congested areas. When the reference checkpoint meets timing, compile time reduction is similar to using the RuntimeOptimized directive as described previously.

In low reuse mode, compile time is not predictable. When the place and route runs get closer to meeting timing, the Vivado tools might increase compile time to meet timing. In other cases, the Vivado tools might decrease compile time if existing placement and routing data is reused efficiently.