Configuration - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

You must first successfully synthesize and implement your design to create a bitstream image. Once the bitstream has been generated and all DRCs are analyzed and corrected, you can load bitstream onto the device using one of the following methods:

Direct Programming

The bitstream is loaded directly to the device using a cable, processor, or custom solution.

Indirect Programming
The bitstream is loaded into an external flash memory. The flash memory then loads the bitstream into the device.

You can use the Vivado tools to accomplish the following:

  • Create the bitstream (.bit or .rbt).
  • Select Tools > Edit Device to review the configuration settings for bitstream generation.
  • Format the bitstream into flash programming files (.mcs).
  • Program the device using either of the following methods:
    • Directly program the device.
    • Indirectly program the attached configuration flash device.

      Flash devices are non-volatile devices and must be erased before programming. Unless a full chip erase is specified, only the address range covered by the assigned MCS is erased.

    Important: The Vivado Design Suite Device Programmer can use JTAG to read the Status register data on Xilinx devices. In case of a configuration failure, the Status register captures the specific error conditions that can help identify the cause of a failure. In addition, the Status register allows you to verify the Mode pin settings M[2:0] and the bus width detect. For details on the Status register, see the Configuration User Guide for your device.
    Tip: If configuration is not successful, you can use a JTAG readback/verify operation on the device to determine whether the intended configuration data was loaded correctly into the device.