Congestion Level Ranges - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

When analyzing congestion, the level reported by the tools can be categorized as shown in the following table.

Note: Congestion levels of 5 or higher often impact QoR and always lead to longer router runtime.
Table 1. Congestion Level Ranges
Level Area Congestion QoR Impact
1, 2 2x2, 4x4 None None
3, 4 8x8, 16x16 Mild Possible QoR degradation
5 32x32 Moderate Likely QoR degradation
6 64x64 High Difficulty routing
7, 8 128x128, 256x256 Impossible Likely unroutable