Constraints on Individual CDC Paths - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

If a CDC bus uses gray-coding (for example, FIFO) or if latency needs to be limited between the two asynchronous clocks on one or more signals, you must use the set_max_delay constraint with the option -datapath_only to ignore clock skew and jitter on these paths, plus override the default path requirement by the latency requirement. It is usually sufficient to use the source clock period for the max delay value, just to ensure that no more than one data is present on the CDC path at any given time.

When the ratio between clock periods is high, choosing the minimum of the source and destination clock periods is also a good option to reduce the transfer latency. A clean asynchronous CDC path should not have any logic between the source and destination sequential cells, so the Max Delay Datapath Only constraint is normally easy to meet for the implementation tools.

Some asynchronous CDC paths require a skew control between the bits of the bus instead of a constraint on the bus latency. Using a bus skew constraint prevents the receiving clock domain from latching multiple states of the bus on the same clock edge. You can set the bus skew constraint on the bus with set_bus_skew command. For example, you can apply set_bus_skew to a CDC bus that uses gray-coding instead of using the Max Delay Datapath Only constraint. For more information, see this link in the Vivado Design Suite User Guide: Using Constraints (UG903).

For the paths that do not need latency control, you can define a point-to-point false path constraint.