Gigabit transceivers (GTs) have specific pinout requirements, and you must consider the following:
- Sharing of reference clocks
- Sharing of PLLs within a quad
- Placement of hard blocks, such as PCIe, and their proximity to transceivers
- In SSI technology devices, crossing of SLR boundaries
Xilinx recommends that you use the GT wizard to generate the core. Alternatively, you can use the Xilinx IP core for the protocol. For pinout recommendations, see the related product guide.
For clock resource balancing, the Vivado placer attempts to constrain loads clocked by GT output clocks (TXOUTCLK or RXOUTCLK) next to the GTs sourcing the clocks. For SSI technology devices, if the GTs are located in the clock regions adjacent to another SLR, the routing resources required for signals entering or exiting SLLs have to compete with the routing resources required by the GT output clock loads. Therefore, GTs located in clock regions next to SLR crossings might reduce the available routing connections to and from the SLL crossings available in those clock regions.