The configuration of the ILA core has an impact in meeting the overall design timing goals. Follow the recommendations below to minimize the impact on timing:
- Choose probe width judiciously. The bigger the probe width the greater the impact on both resource utilization and timing.
- Choose ILA core data depth judiciously. The bigger the data depth the greater the impact on both block RAM resource utilization and timing.
- Ensure that the clocks chosen for the ILA cores are free-running clocks. Failure to do so could result in an inability to communicate with the debug core when the design is loaded onto the device.
- Ensure that the clock going to the
dbg_hubis a free running clock. Failure to do so could result in an inability to communicate with the debug core when the design is loaded onto the device. You can use the
connect_debug_portTcl command to connect the
clkpin of the debug hub to a free-running clock.
- Close timing on the design prior to adding the debug cores. Xilinx does not recommend using the debug cores to debug timing related issues.
- If you still notice that timing has degraded due to adding
the ILA debug core and the critical path is in the
dbg_hub, perform the following steps:
- Open the synthesized design.
- Find the
dbg_hubcell in the netlist.
- Go to the Properties window of the
- Find property C_CLK_INPUT_FREQ_HZ.
- Set it to frequency (in Hz) of the clock that is connected
- Find property C_ENABLE_CLK_DIVIDER and enable it.
- Re-implement design.
Make sure the clock input to the ILA core is synchronous to the signals being probed. Failure to do so results in timing issues and communication failures with the debug core when the design is programmed into the device.
- Make sure that the design meets timing before running it on hardware. Failure to do so results in unreliable probed waveforms.
The following table shows the impact of using specific ILA features on design timing and resources.
|ILA Feature||When to Use||Timing||Area|
|Capture Control/ Storage Qualification||
To capture relevant data
To make efficient use of data capture storage (block RAM)
|Medium to High Impact||
When BASIC trigger conditions are insufficient
To use complex triggering to focus in on problem area
Number of Comparators per Probe Port
Note: Maximum is 4.
To use probe in multiple conditionals:
|Medium to High Impact||
|Data Depth||To capture more data samples||High Impact||
|ILA Probe Port Width||To debug a large bus versus a scalar||Medium Impact||
|Number of Probes Ports||To probe many nets||Low Impact||