For ISERDESE3 and IDDRE1 clocking in UltraScale and UltraScale+ devices, maximum skew requirements exist between the clock and inverted clock pins. To meet the maximum skew requirements, Xilinx recommends using a single net for the clock and inverted clock pins when using the local inversion.
In the following figure, the left side shows a suboptimal configuration that uses the CLKOUT0B output of the MMCM. The right side of the figure shows the optimal configuration that uses the local inversion on the CLK_B and CB pins of the ISERDESE3 and IDDRE1. Using the optimal configuration guarantees that the maximum skew requirement is met while using fewer global clock resources.