Mapping Memories to UltraRAM Blocks - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

UltraRAM is a 4Kx72 memory block with two ports using a single clock. This primitive is only available in certain UltraScale+™ devices. In these devices, UltraRAM is included in addition to block RAM resources.

UltraRAM can be used in your design using one of the following methods:

  • Rely on synthesis to infer UltraRAMs by setting the ram_style = "ultra" attribute on a memory declaration in HDL.
  • Instantiate Xilinx XPM_MEMORY primitives.
  • Instantiate UltraRAM UNISIM primitives.

The following code example shows the instantiation of XPM memory and is available in the HDL Language templates. Highlighted parameters MEMORY_PRIMITIVE and READ_LATENCY are the key parameters to infer memory as UltraRAM for high performance.

  • MEMORY_PRIMITIVE = "ultra" specifies the memory is to be inferred as UltraRAM.
  • READ_LATENCY defines the number of pipeline registers present on the output of the memory.

Larger memories are mapped to an UltraRAM matrix consisting of multiple UltraRAM cells configured as row x column structures.

A matrix can be created with single or multiple columns based on the depth. The current default threshold for UltraRAM column height is 8 and it can be controlled with the attribute CASCADE_HEIGHT.

The difference between single column and multiple column UltraRAM matrix is as follows:

  • Single column UltraRAM matrix uses the built-in hardware cascade without fabric logic.
  • Multiple column UltraRAM matrix uses built-in hardware cascade within each column, plus some fabric logic for connecting the columns. Extra pipelining may be required to maintain performance. This is inferred by increasing the read latency. The Vivado tools automatically pack these registers into UltraRAM as required.
    Figure 1. Specifying UltraRAM in RTL Code (via XPM)

The preceding example uses a 32 K x 72 memory configuration, which uses eight UltraRAMs. To increase performance of the UltraRAM, more pipelining registers should be added to the cascade chain. This is achieved by increasing the read latency integer.

For more information on inferring UltraRAM in Vivado synthesis, see this link in the Vivado Design Suite User Guide: Synthesis (UG901).