Opening the Synthesized Design - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

The first steps after synthesis are to read the netlist from the synthesized design into memory and apply design constraints. You can open the synthesized design in various ways, depending on the flow used. For more information, see this link in the Vivado Design Suite User Guide: Implementation (UG904).