Optimizing for MTBF - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

The total MTBF of a design is a function of:

  • Synchronizer MTBF
  • Device failure in time (FIT) rate due to single-event upsets (SEUs)
Note: The device FIT rate due to SEUs largely depends on process and device size.

The synchronizer MTBF is design dependent and varies with the following:

  • Number of asynchronous CDC points
  • Number of synchronizer stages at each crossing point
  • Frequency of the destination FF
  • Toggle rate of the source