Given the importance of power, the Vivado tools support methods for obtaining an accurate estimate for power, as well as providing some power optimization capabilities. For additional information, see the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907).
Recommended: When targeting UltraScale and UltraScale+™ devices and using the Explore directives or Explore-based strategies, you must manually enable block RAM power optimization by running
opt_designruns. Xilinx recommends minimizing memory resources to reduce power. Review the bit utilization from the RAM Utilization Report to find memory arrays with inefficient mapping. Also consider using the HDL RAM_STYLE MIXED attribute for the most efficient mapping of arrays using a combination of block memory and LUTRAMs.