Power Rail Consolidation Impacting Power - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

To take advantage of the power management switching of power domains, your design must keep some discrete power rails. This allows individual rails to be powered off with the power domain switching logic at the cost of using additional voltage regulators or regulator outputs. For more information, see this link in the UltraScale Architecture PCB Design User Guide (UG583).

Tip: The Vivado tools also support power rail constraints. For information, see this link in the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907).