Route Compile Time - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

You can use the route_design -ultrathreads option to reduce compile time at the expense of repeatability. This option gives the router extra freedom to execute multiple threads, which allows routing to finish faster but with slightly different results each time. The slack between identical subsequent runs differs by a fractional percentage, but the compile time savings are significant. Consider this option to reduce router compile time only if your environment does not require strictly repeatable results.