Running Debug-Related DRCs - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

The Vivado Design Suite provides debug-related DRCs, which are selected as part of the default rule deck when report_drc is run. The DRCs check for the following:

  • Block RAM resources for the device are exceeded because of the current requirements of the debug core.
  • Non-clock net is connected to the clock port on the debug core.
  • Port on the debug core is unconnected.