Power optimization works on the entire design or on portions of the design
set_power_opt is used) to minimize power
Power optimization can be run either pre-place or post-place in the design flow, but not both. The pre-place power optimization step focuses on maximizing power saving. This can result (in rare cases) in timing degradation. If preserving timing is the primary goal, Xilinx recommends the post-place power optimization step. This step performs only those power optimizations that preserve timing.
In cases where portions of the design should be preserved due to legacy
(IP) or timing considerations, use the
command to exclude those portions (such as specific hierarchies, clock domains, or cell
types) and rerun power optimization.