Synchronous CDC - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
Release Date
2022.1 English

When the design includes synchronous CDC paths between clocks that originate from the same MMCM/PLL, you can use the following techniques to better control the clock insertion delays and skew and therefore, the slack on those paths.

Important: If the CDC paths are between clocks that originate from different MMCM/PLLs, the clock insertion delays across the MMCMs/PLLs are more difficult to control. In this case, Xilinx recommends that you treat these clock domain crossings as asynchronous and make design changes accordingly.

When a path is timed between two clocks that originate from different output pins of the same MMCM/PLL, the MMCM/PLL phase error adds to the clock uncertainty for the path. For designs using high clock frequencies, the phase error can cause issues with timing closure both for setup and hold.

The following figure shows an example of paths both with and without the phase error. Path 1 is a CDC path clocked by two buffers connected to the same MMCM output and does not include the phase error. Path 2 is clocked by two clocks that originate from two different MMCM outputs and does include the phase error.

Figure 1. MMCM and Phase Error

When two synchronous clocks from the same MMCM/PLL have a simple period ratio (/2 /4 /8), you can prevent the phase error between the two clock domains using a single MMCM/PLL output connected to two BUFGCE_DIV buffers. The BUFGCE_DIV buffer performs the clock division (/1 /2 /4 /8). Other ratios are possible (/3 /5 /6 /7) but this requires modifying the clock duty cycle and making mixed edge timing paths more challenging.

Note: Because the BUFGCE and BUFGCE_DIV do not have the same cell delays, Xilinx recommends using the same clock buffer for both synchronous clocks (two BUFGCE or two BUFGCE_DIV buffers).

The following figure shows two BUFGCE_DIVs that divide the CLKOUT0 clock by 1 and by 2 respectively.

Important: To ensure safe timing between parallel BUFGCE_DIV cells where the BUFGCE_DIVIDE property is set to a value greater than 1, both buffers must use the same enable signal (CE) and the same reset signal (RST). Otherwise, the divided clocks might become phase shifted from one another in hardware, which is not reported by the Vivado tools.
Figure 2. MMCM Synchronous CDC with BUFGCE_DIVs Connected to One MMCM Output

To automatically balance several clocks that originate from the same MMCM or PLL, set the same CLOCK_DELAY_GROUP property value on the nets driven by the clock buffers that need to be balanced. Following are additional recommendation:

  • Avoid setting the CLOCK_DELAY_GROUP constraint on too many clocks, because this stresses the clock placer resulting in suboptimal solutions or errors.
  • Review the critical synchronous CDC paths in the Timing Summary Report to determine which clocks must be delay matched to meet timing.
  • Limit the use of the CLOCK_DELAY_GROUP on groups of synchronous clocks with tight requirements and with identical clocking topologies.
    Important: Xilinx recommends using the Clocking Wizard for creating optimal clocking structures, which use a mix of BUFGCEs and BUFGCE_DIVs along with related clock grouping constraints.