Use Cell Bloating - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

You can use cell bloating to insert whitespace (increased cell spacing) during the place_design step. This leads to a lower density of cells in a given area of the die, which can reduce congestion by increasing available routing. This technique is particularly effective in small, congested areas of relatively high-performance logic.

To use cell bloating, apply the CELL_BLOAT_FACTOR property to hierarchical cells and set the value to LOW, MEDIUM, or HIGH. When working with smaller modules of several hundred cells, HIGH is the recommended setting.

CAUTION:
If the device already uses too many routing resources, cell bloating is not recommended. In addition, using cell bloating on larger cells might force placed cells to be too far apart.