Whether you use soft SLR floorplan constraints, hard SLR floorplan constraints, or no floorplan constraints, the number of pipeline stages required to meet timing between major portions of the design located in different SLRs varies based on the following:
- Target frequency
- Device floorplan
- Device speed grade
You can leverage the auto-pipelining feature to allow the placer algorithms to decide on the number of required stages and their optimal location, which helps timing closure across SLR boundaries. When using this feature, the Vivado placer automatically uses Laguna registers without additional intervention.
You can enable auto-pipelining by setting AUTOPIPELINING_* attributes on buses and handshake logic in your RTL, but make sure that the additional latency does not adversely affect the design functionality. Alternatively, you can use the Xilinx AXI Register Slice Memory Mapped or Streaming IP, configured in the SLR crossing.