Using Horizontal Clock Region Buffers for Clock Gating - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

You can use the Horizontal Clock Region Buffer (BUFHCE) with BUFGs to perform a medium-grained clock gating function. For portions of a clock domain ranging from a few hundred to a few thousand loads in which you want to stop clocking intermittently, the BUFHCE can be an effective clocking resource. A BUFG can drive multiple BUFHCEs in the same or different clock regions, which allows you to individually control clocking in several low clock skew domains.

Figure 1. Horizontal Clock Region Buffers

When used independently, all loads connected to the BUFH must reside in the same clock region. This makes it well-suited for very high-speed, more fine-grained (fewer loads) clocking needs. BUFHCE can be used to achieve medium-grained clock-gating within the specific clock region. You must ensure that the resources driven by the BUFH do not exceed the available resources in the clock region and that no other conflicts exist.

The phase relationship might be different between the BUFH and clock domains driven by BUFGs, other BUFHs, or any other clocking resource. The single exception is when two BUFHs are driven to horizontally adjacent regions. In this case, the skew between left and right clock regions when both BUFHs driven by the same clock source should have a very controlled phase relationship in which data may safely cross the two BUFH clock domains. BUFHs can be used to gain access to MMCMs or PLLs in opposite regions to a clock input or GT. However, care must be taken in this approach to ensure that the MMCM or PLL is available.