Using Soft SLR Floorplan Constraints - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

For large designs, logic for most of the major blocks fits in one SLR as expected and closes timing after a few design iterations. However, small portions of the logic, especially the connectivity across major blocks and across SLRs, is subject to QoR variation depending on the overall design placement. In such cases, the placer and physical optimization algorithms need additional flexibility to replicate or move some of the logic to a different SLR to address placement challenges and close timing.

You can use the USER_SLR_ASSIGNMENT property to floorplan the design by assigning large design blocks to SLRs. Set this property to a string value, which is applied to hierarchical cells and ignored on leaf cells. The value you set for this property influences the logic partitioning as follows:

SLR name
When a hierarchical cell is assigned the name of an SLR (SLR0, SLR1, SLR2, etc.), the placer attempts to place the entire cell within the specified SLR.
String value
When a hierarchical cell is assigned an arbitrary string value, the placer chooses the SLR. This prevents cells from being partitioned into multiple SLRs.
Note: If multiple cells have the same USER_SLR_ASSIGNMENT value, the placer attempts to group the cells in the same SLR.

The USER_SLR_ASSIGNMENT property is a soft constraint during SLR partitioning while the Pblock is always a hard constraint during SLR partitioning and global placement. Unlike Pblocks, the USER_SLR_ASSIGNMENT can be ignored by the placer to find a valid SLR partitioning of the design. Both USER_SLR_ASSIGNMENT and Pblocks allow the detailed placer and physical optimization to make fine-tuned adjustments to leaf cell placement near the SLR boundaries to improve timing. These adjustments include moving pipeline registers across SLR boundaries if the moves improve timing. These register moves are not permitted across Pblock boundaries.

In the following example, a design contains three timing-critical hierarchical blocks with cell names IP1, IP2, and IP3 and targets a two-SLR device. To split the three blocks so that IP1 and IP2 are kept together in SLR1 while IP3 is placed in SLR0, the following XDC constraints are applied:

set_property USER_SLR_ASSIGNMENT SLR1 [get_cells {IP1 IP2}]
set_property USER_SLR_ASSIGNMENT SLR0 [get_cells IP3]

The following figure shows the resulting placement. To improve performance, you can incorporate extra pipeline stages to traverse distances within the device. This is particularly helpful along expected SLR crossings, between IP2 and IP3 in this example. During detail placement and phys_opt_design, the pipeline registers from IP2 and IP3 can automatically move across SLR boundaries if this improves timing.

Figure 1. Placement Example for the USER_SLR_ASSIGNMENT Property

For cases in which you cannot set USER_SLR_ASSIGNMENT or the placer splits challenging paths across SLRs, you can use the USER_CROSSING_SLR property to direct where SLR crossings should or should not occur. Typically, you apply this property to nets or leaf pins where you want pins to be placed in the same SLR as the net driver, or where you want the SLR crossing for the case of a register chain. Set this property to a Boolean value, which is applied to nets and pins to constrain individual SLR crossings:

Indicates that the target net object should cross an SLR or the target pin object should be connected across an SLR. You can only apply the TRUE value to register-to-register connections with a single fanout in between.
Note: You cannot use the TRUE value for random logic. This option is useful for ensuring a chain of registers always crosses a SLR boundary on a specific register when trying multiple implementation strategies.
Indicates that the target net object should not cross an SLR or the target pin object should not be connected across an SLR. You can apply the FALSE value to any net or pin.
Note: Pins must not be inside macro primitives, because these pins are internal and cannot be constrained.

In the following example, a pipeline register chain crosses an SLR twice, resulting in an unintentional, inefficient zigzag path.

Note: In the next two figures, each dot represents a register stage.
Figure 2. Suboptimal SLR Crossings Before Setting the USER_CROSSING_SLR Property

To achieve the optimal placement in which only net_B crosses the SLR, the following XDC constraints are applied:

set_property USER_CROSSING_SLR FALSE [get_pins -leaf -of [get_nets net_A]]
set_property USER_CROSSING_SLR TRUE [get_pins -leaf -of [get_nets net_B]]

The resulting placement contains just a single SLR crossing on net_B as shown in the following figure.

Figure 3. Optimal SLR Crossings After Setting the USER_CROSSING_SLR Property