Using VIO Cores - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

The Virtual Input/Output (VIO) core allows you to monitor and drive internal device signals in real time. Use this core when it is necessary to drive or monitor low speed signals, such as resets or status signals. The VIO debug core must be instantiated in the design and can be used in both Vivado IP integrator block design and RTL. The VIO core is available in the IP catalog for RTL-based designs and in IP integrator.

For information on customizing the VIO core, see the Virtual Input/Output LogiCORE IP Product Guide (PG159). For information on taking measurements with a VIO core, see this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).