Xilinx tools assist in interactive design planning and pin selection. These tools are only as effective as the information you provide them. Tools such as the Vivado I/O Planner can assist pinout efforts. These tools can graphically display the I/O placement, show relationships among clocks and I/O components, and provide DRCs to analyze pin selection.
If a design version is available, a quick top-level floorplan can be created to analyze the data flow through the device. For more information, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).