You can use the USER_CLOCK_ROOT property to force the clock root location of a clock driven by a clock buffer. Specifying the USER_CLOCK_ROOT property influences the design placement, because it impacts both insertion delay and skew by modifying the clock routing. The USER_CLOCK_ROOT value corresponds to a clock region, and you must set the property on the net segment directly driven by the high fanout clock buffer. Following is an example:
set_property USER_CLOCK_ROOT X2Y3 [get_nets clkgen/wbClk_o]
After placement, you can use the CLOCK_ROOT property to query the actual clock root as shown in the following example. The CLOCK_ROOT reports the assigned root whether it was user assigned or automatically assigned by the Vivado tools.
get_property CLOCK_ROOT [get_nets clkgen/wbClk_o] => X2Y3
Another way to review the clock root assignments of your implemented design is to use the
report_clock_utilization Tcl command. For example:
The following figure shows this report.