Using the UltraFast Design Methodology Checklist - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

To take full advantage of the UltraFast design methodology, use this guide with the UltraFast Design Methodology Checklist (XTP301). The checklist is available from the Xilinx Documentation Navigator or as a standalone spreadsheet.

The questions in the UltraFast Design Methodology Checklist highlight typical areas in which design decisions are likely to have downstream impact and draw attention to issues that are often overlooked or ignored. Each tab in the checklist:

  • Targets a specific role within a typical design team.
  • Includes common questions and recommended actions to take during each design flow step, including project planning, board and device planning, IP and submodule design, and top-level design closure.
  • Includes a Documentation and Training section that lists resources related to the design flow step.
  • Provides links to content in this guide or other Xilinx documentation, which offer guidance on addressing the design concerns raised by the questions.