Valid Startpoints and Endpoints - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

Path segmentation is reported by the tools in the log file when the constraints are applied. You must avoid it by using valid startpoints and endpoints:

Clock, clock pin, sequential cell (implies valid startpoint pins of the cell), input or inout port.
Clock, input data pin of sequential cell, sequential cell (implies valid endpoint pins of the cell), output or inout port.

For details on path segmentation, see this link in the Vivado Design Suite User Guide: Using Constraints (UG903).