Verifying Clocks Definition and Coverage - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

When all design clocks are defined and applied in memory, you can verify the waveform of each clock, the relationship between master and generated clocks by using the report_clocks command:

Clock Period Waveform Attributes Sources
sysClk 10.00000 {0.00000 5.00000} P {sysClk}
clkfbout 10.00000 {0.00000 5.00000} P,G {clkgen/mmcm_adv_inst/CLKFBOUT}
cpuClk 20.00000 {0.00000 10.00000} P,G {clkgen/mmcm_adv_inst/CLKOUT0}
Generated Clocks
Generated Clock : cpuClk
Master Source : clkgen/mmcm_adv_inst/CLKIN1
Master Clock : sysClk
Edges : {1 2 3}
Edge Shifts : {0.000 5.000 10.000}
Generated Sources : {clkgen/mmcm_adv_inst/CLKOUT0}

You can also verify that all internal timing paths are covered by at least one clock. The Check Timing report provides two checks for that purpose:

Reports any active clock pin that is not reached by a defined clock.
Reports all the data input pins of sequential cells that have a timing check relative to a clock but the clock has not been defined.

If both checks return zero, the timing analysis coverage will be high.

Alternatively, you can run the XDC and Timing Methodology checks to verify that all clocks are defined on recommended netlist objects without introducing any constraint conflict or inaccurate timing analysis scenario.

Use the following command to run these checks:

report_methodology -checks [get_methodology_checks {TIMING-* XDC*}]