Primitive: KEEPER Symbol
The design element is a weak keeper element that retains the value of the net connected to its bidirectional O pin. For example, if a logic 1 is being driven onto the net, KEEPER drives a weak/resistive 1 onto the net. If the net driver is then 3-stated, KEEPER continues to drive a weak/resistive 1 onto the net.
Design Entry Method
This element can be connected to a net in the following locations on a top-level schematic file:
A net connected to an input IO Marker.
A net connected to both an output IO Marker and 3-statable IO element, such as an OBUFT.
VHDL Instantiation Template
Library UNISIM; use UNISIM.vcomponents.all;
-- KEEPER: I/O Buffer Weak Keeper -- 7 Series -- Xilinx HDL Language Template, version 2022.1 KEEPER_inst : KEEPER port map ( O => O -- Keeper output (connect directly to top-level port) ); -- End of KEEPER_inst instantiation
Verilog Instantiation Template
// KEEPER: I/O Buffer Weak Keeper // 7 Series // Xilinx HDL Language Template, version 2022.1 KEEPER KEEPER_inst ( .O(O) // Keeper output (connect directly to top-level port) ); // End of KEEPER_inst instantiation
- See the 7 Series FPGA SelectIO Resources User Guide (UG471).