Primitive: 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)
This design element is a 128-bit deep by 1-bit wide random access memory and has a read/write port that writes the value on the D input data pin when the write enable (WE) is high to the memory cell specified by the A address bus. This happens shortly after the rising edge of the WCLK and that same value is reflected in the data output SPO. When WE is low, an asynchronous read is initiated in which the contents of the memory cell specified by the A address bus is output asynchronously to the SPO output. The read port can perform asynchronous read access of the memory by changing the value of the address bus DPRA, and by outputting that value to the DPO data output.
|SPO||Output||1||Read/Write port data output addressed by A.|
|DPO||Output||1||Read port data output addressed by DPRA.|
|D||Input||1||Write data input addressed by A.|
|A||Input||7||Read/Write port address bus.|
|DPRA||Input||7||Read port address bus.|
|WCLK||Input||1||Write clock (reads are asynchronous).|
If instantiated, the following connections should be made to this component:
Tie the WCLK input to the desired clock source, the D input to the data source to be stored and the DPO output to an FDCE D input or other appropriate data destination.
Optionally, the SPO output can also be connected to the appropriate data destination or else left unconnected.
Connect the WE clock enable pin to the proper write enable source in the design.
Connect the 7-bit A bus to the source for the read/write addressing and the 7-bit DPRA bus to the appropriate read address connections.
You can use the INIT attribute to specify the initial contents of the RAM. If left unspecified, the initial contents default to all zeros.
Design Entry Method
|INIT||HEX||Any 128-bit value||All zeros||Specifies the initial contents of the RAM.|
VHDL Instantiation Template
Library UNISIM; use UNISIM.vcomponents.all;
-- RAM128X1D: 128-deep by 1-wide positive edge write, asynchronous read -- dual-port distributed LUT RAM (Mapped to two SliceM LUT6s) -- 7 Series -- Xilinx HDL Language Template, version 2022.1 RAM128X1D_inst : RAM128X1D generic map ( INIT => X"00000000000000000000000000000000") port map ( DPO => DPO, -- Read/Write port 1-bit ouput SPO => SPO, -- Read port 1-bit output A => A, -- Read/Write port 7-bit address input D => D, -- RAM data input DPRA => DPRA, -- Read port 7-bit address input WCLK => WCLK, -- Write clock input WE => WE -- RAM data input ); -- End of RAM128X1D_inst instantiation
Verilog Instantiation Template
// RAM128X1D: 128-deep by 1-wide positive edge write, asynchronous read (Mapped to two SliceM LUT6s) // dual-port distributed LUT RAM // 7 Series // Xilinx HDL Language Template, version 2022.1 RAM128X1D #( .INIT(128'h00000000000000000000000000000000) ) RAM128X1D_inst ( .DPO(DPO), // Read port 1-bit output .SPO(SPO), // Read/write port 1-bit output .A(A), // Read/write port 7-bit address input .D(D), // RAM data input .DPRA(DPRA), // Read port 7-bit address input .WCLK(WCLK), // Write clock input .WE(WE) // Write enable input ); // End of RAM128X1D_inst instantiation
- See the 7 Series FPGAs Configurable Logic Block User Guide (UG474).