This section describes the unimacros that can be used with 7 series FPGAs and Zynq®-7000 SoC devices devices. The unimacros are organized alphabetically.
The following information is provided for each unimacro, where applicable:
- Name and description
- Schematic symbol
- Logic table (if any)
- Port descriptions
- Design Entry Method
- Available attributes
- Example instantiation templates
- Links to additional information
Instantiation templates for library elements are also available in Vivado, as well as in a downloadable ZIP file. Because PDF includes headers and footers if you copy text that spans pages, you should copy templates from Vivado or the downloaded ZIP file whenever possible.
Instantiation templates can be found on the Web in the Instantiation Templates for 7 Series Devices file.
List of UniMacros
|BRAM_SDP_MACRO||Macro: Simple Dual Port RAM|
|BRAM_SINGLE_MACRO||Macro: Single Port RAM|
|BRAM_TDP_MACRO||Macro: True Dual Port RAM|
|COUNTER_LOAD_MACRO||Macro: Loadable Counter|
|COUNTER_TC_MACRO||Macro: Counter with Terminal Count|
|EQ_COMPARE_MACRO||Macro: Equality Comparator|
|FIFO_DUALCLOCK_MACRO||Macro: Dual Clock First-In, First-Out (FIFO) RAM Buffer|
|FIFO_SYNC_MACRO||Macro: Synchronous First-In, First-Out (FIFO) RAM Buffer|