This tutorial includes four labs that demonstrate different features of the Xilinx® Vivado Design Suite implementation tool:
- Lab 1 demonstrates using implementation strategies to meet different design objectives.
- Lab 2 demonstrates the use of the incremental compile feature after making a small design change.
- Lab 3 demonstrates the use of manual placement and routing, and duplicated routing, to fine-tune the timing on the design.
- Lab 4 demonstrates the use of the Vivado ECO to make quick changes to your design post implementation.
Vivado implementation includes all steps necessary to place and route the netlist onto the FPGA device resources, while meeting the logical, physical, and timing constraints of a design.