In this lab, you will learn how to use the Vivado® Engineering Change Order (ECO) flow to modify your design post implementation, implement the changes, run reports on the changed netlist, and generate programming files.
For this lab, you will use the design file that is included with this guide and is targeted at the Kintex® UltraScale™ KCU105 Evaluation Platform. For instructions on locating the design files, see Locating Design Files for Lab 4.
A block diagram of the design is shown in the following figure.
In this design, a mixed-mode clock manager (MMCM) is used to synthesize a 100 MHz clock from the 300 MHz clock provided by the board.
A 29-bit counter is used to divide the clock down further. The four most
significant bits of the counter form the
count<3:0> signal that is 0-extended to 8 bits and drives the 8
on-board LEDs through an 8-bit 2-1 mux.
count<3:0> signal is also
squared using a multiplier, and the product drives the other eight inputs of the mux. A
Toggle signal controls the mux select and either
drives the LEDs (shown in the following figure) with the counter value or the multiplier
Pause signal allows you to stop the
counter, and a
Reset signal allows you to reset the
Reset signals can either be
controlled from on-board buttons shown in the following figure or a VIO in the Hardware
Manager as shown in the subsequent figure. The VIO also allows you to observe the status
of the LEDs. The following figures show the location of the push-buttons and the LEDs on
the KCU105 board and a Hardware Manager dashboard. These allow you to control the push
button and observe the LEDs through the VIO.