Step 5: Using Manual Routing to Reduce Clock Skew

In the Tcl Console, type the following command:

for {set i 14} {$i<32} {incr i} { 
   puts "$i [get_property ROUTE [get_nets -of [get_pins -of \
   [get_cells wbOutputData_reg[$i]] -filter DIRECTION==OUT]]]"
}

This for loop initializes the index to 14 (set i 14), and gets the ROUTE property to return the details of the route on each selected net.

The Tcl Console returns the net index followed by relative route information for each net:

14  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC0_D1 LIOI_OLOGIC0_OQ LIOI_O0 }  
15  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC1_D1 LIOI_OLOGIC1_OQ LIOI_O1 }  
16  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC0_D1 LIOI_OLOGIC0_OQ LIOI_O0 }  
17  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC1_D1 LIOI_OLOGIC1_OQ LIOI_O1 }  
18  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC0_D1 LIOI_OLOGIC0_OQ LIOI_O0 }  
19  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC1_D1 LIOI_OLOGIC1_OQ LIOI_O1 }  
20  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC0_D1 LIOI_OLOGIC0_OQ LIOI_O0 }  
21  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC1_D1 LIOI_OLOGIC1_OQ LIOI_O1 }  
22  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC0_D1 LIOI_OLOGIC0_OQ LIOI_O0 }  
23  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC1_D1 LIOI_OLOGIC1_OQ LIOI_O1 }  
24  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC0_D1 LIOI_OLOGIC0_OQ LIOI_O0 }  
25  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC1_D1 LIOI_OLOGIC1_OQ LIOI_O1 }  
26  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC0_D1 LIOI_OLOGIC0_OQ LIOI_O0 }  
27  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC1_D1 LIOI_OLOGIC1_OQ LIOI_O1 }  
28  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC0_D1 LIOI_OLOGIC0_OQ LIOI_O0 }  
29  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC1_D1 LIOI_OLOGIC1_OQ LIOI_O1 }  
30  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC0_D1 LIOI_OLOGIC0_OQ LIOI_O0 }  
31  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 WW2BEG0 IMUX_L34 IOI_OLOGIC1_D1 LIOI_OLOGIC1_OQ LIOI_O1 }

From the returned ROUTE properties, note that the nets are routed from the output registers using identical resources, up to node IMUX_L34. Beyond that, the Vivado router uses different nodes for odd and even index nets to complete the connection to the die pad.

By reusing routing paths, you can manually route one net with an even index, like wbOutputData_OBUF[14], and one net with an odd index, such as wbOutputData_OBUF[15], and copy the routing to all other even and odd index nets in the group.

In the Tcl Console, select the first net with the following command:

select_objects [get_nets -of [get_pins -of \
[get_cells wbOutputData_reg[14]] -filter DIRECTION==OUT]]

In the Device window, right-click to open the popup menu and select Unroute.

Click Yes in the Confirm Unroute dialog box.

The Device window displays the unrouted net as a fly-line between the register and the output pad.

Click the Maximize button

to maximize the Device window.

Right-click the net and select Enter Assign Routing Mode.

The Target Load Cell Pin dialog box opens, as seen in the following Figure, to let you select a load pin to route to or from. In this case, only one load pin populates: wbOutputData_OBUF[14]_inst.

Select the load cell pin wbOutputData_OBUF[14]_inst/I, and click OK.

The Vivado IDE enters into Assign Routing mode, displaying a new Routing Assignment window on the right side of the Device window, as shown in the following figure.

The Routing Assignment window includes the following sections:

Net

Displays the current net being routed.

Options

Are hidden by default, and can be displayed by clicking Options.

Number of hops: Defines how many programmable interconnect points, or PIPs, to look at when reporting the available neighbors. The default is 1.
Maximum number of neighbors: Limits the number of neighbors displayed for selection.
Allow overlap with unfixed nets: Enables or disables a loose style of routing which can create conflicts that must be later resolved. The default is ON.

Neighbor Nodes

Lists the available neighbor PIPs/nodes to choose from when defining the path of the route.

Assigned Nodes

Shows the currently assigned nodes in the route path of the selected net.

Assign Routing

Assigns the currently defined path in the Routing Assignment window as the route path for the selected net.

Exit Mode

Closes the Routing Assignment window.

The Assigned Nodes section displays six currently assigned nodes. The Vivado router automatically assigns a node if it is the only neighbor of a selected node and there are no alternatives to the assigned nodes for the route. In the Device window, the assigned nodes appear as a partial route in orange.

In the currently selected net, wbOutputData_OBUF[14], nodes CLBLL_LL_AQ and CLBLL_LOGIC_OUTS4 are already assigned because they are the only neighbor nodes available to the output register, wbOutputData_reg[14]. The nodes IMUX_L34, IOI_OLOGIC0_D1, LIOI_OLOGIC0_OQ, and LIOI_O0 are also already assigned because they are the only neighbor nodes available to the destination, the output buffer (OBUF).

A gap exists between the two routed portions of the path where there are multiple neighbors to choose from when defining a route. This gap is where you will use manual routing to complete the path and add the needed delay to balance the clock skew.

You can route the gap by selecting a node on either side of the gap and then choosing the neighbor node to assign the route to. Selecting the node displays possible neighbor nodes in the Neighbor Nodes section of the Routing Assignment window and appear as dashed white lines in the Device window.

Tip: The number of reachable neighbor nodes displayed depends on the number of hops defined in the Options.

Under the Assigned Nodes section, select the CLBLL_LOGIC_OUTS4 node before the gap.

The available neighbors appear as shown in the following figure.

To add delay to compensate for the clock skew, select a neighbor node that provides a slight detour over the more direct route previously chosen by the router.

Under Neighbor Nodes, select node NE2BEG0.

This node provides a routing detour to add delay, as compared to some other nodes such as WW2BEG0, which provide a more direct route toward the output buffer. Clicking a neighbor node once selects it so you can explore routing alternatives. Double-clicking the node temporarily assigns it to the net, so that you can then select the next neighbor from that node.

In Neighbor Nodes, assign node NE2BEG0 by double-clicking it.

This adds the node to the Assigned Nodes section of the Routing Assignment window, which updates the Neighbor Nodes.

In Neighbor Nodes, select and assign nodes WR1BEG1, and then WR1BEG2.

Tip: In case you assigned the wrong node, you can select the node from the Assigned Nodes list, right-click, and select Remove on the context menu.

You can turn off the Auto Fit Selection in the Device window if you would like to stay at the same zoom level.

The following figure shows the partially routed path using the selected nodes shown in orange. You can use the automatic routing feature to fill the remaining gap.

Under the Assigned Nodes section of the Routing Assignment window, right-click the Net Gap, and select Auto-Route, as shown in the following figure.

The Vivado router fills in the last small bit of the gap. With the route path fully defined, you can assign the routing to commit the changes to the design.

Click Assign Routing at the bottom of the Routing Assignment window.

The Assign Routing dialog box opens, as seen in the following figure. This displays the list of currently assigned nodes that define the route path. You can select any of the listed nodes, highlighting it in the Device window. This lets you quickly review the route path prior to committing it to the design.

Make sure Fix Routing is checked, and click OK.

The Fix Routing checkbox marks the defined route as fixed to prevent the Vivado router from ripping it up or modifying it during subsequent routing steps. This is important in this case, because you are routing the net manually to add delay to match clock skew.

Examine the Tcl commands in the Tcl Console.

The Tcl Console reports any Tcl commands that assigned the routing for the current net. Those commands are:

set_property is_bel_fixed 1 [get_cells {wbOutputData_reg[14] wbOutputData_OBUF[14]_inst }]
set_property is_loc_fixed 1 [get_cells {wbOutputData_reg[14] wbOutputData_OBUF[14]_inst }]
set_property fixed_route {  { CLBLL_LL_AQ CLBLL_LOGIC_OUTS4 NE2BEG0 WR1BEG1 WR1BEG2 SW2BEG1 IMUX_L34 IOI_OLOGIC0_D1 LIOI_OLOGIC0_OQ LIOI_O0 }  } [get_nets {wbOutputData_OBUF[14]}]

Important: The FIXED_ROUTE property assigned to the net, wbOutputData_OBUF[14], uses a directed routing string with a relative format, based on the placement of the net driver. This lets you reuse defined routing by copying the FIXED_ROUTE property onto other nets that use the same relative route.

After defining the manual route for the even index nets, the next step is to define the route path for the odd index net, wbOutputData_OBUF[15], applying the same steps you just completed.

In the Tcl Console type the following to select the net:

select_objects [get_nets wbOutputData_OBUF[15]]

With the net selected:

Unroute the net.
Enter Routing Assignment mode.
Select the load cell pin.
Route the net using the specified neighbor nodes (NE2BEG0, WR1BEG1, and WR1BEG2).
Auto-Route the gap.
Assign the routing.

The Assign Routing dialog box, shown in the following figure, shows the nodes selected to complete the route path for the odd index nets.

You routed the wbOutputData_OBUF[14] and wbOutputData_OBUF[15] nets with the detour to add the needed delay. You can now run the Report Datasheet command again to examine the timing for these nets with respect to the lower order bits of the bus.

Switch to the Timing Datasheet report window. Notice the information message in the banner of the window indicating that the report is out of date because the design was modified.

In the Timing Datasheet report, click Rerun to update the report with the latest timing information.

Select Max/Min Delays for Groups > Clocked by wbClk > wbOutputData[0] to display the timing info for the wbOutputData bus, as seen in the following figure.

You can see from the report that the skew within the rerouted nets, wbOutputData[14] and wbOutputData[15], more closely matches the timing of the lower bits of the output bus, wbOutputData[13:0]. The skew is within the target of 100 ps of the reference pin wbOutputData[0].

In Step 6, you copy the same route path to the remaining nets, wbOutputData_OBUF[31:16], to tighten the timing of the whole wbOutputData bus.

Step 5: Using Manual Routing to Reduce Clock Skew - 2022.1 English

Vivado Design Suite Tutorial: Implementation (UG986)