The design used for Lab 1 is the CPU Netlist example design,
project_cpu_netlist_kintex7, provided with the Vivado Design Suite installation. This design uses a
top-level EDIF netlist source file, and an XDC constraints file.
The design used for Lab 2 and Lab 3 is the BFT Core example design,
project_bft_kintex7. This design includes both Verilog and
VHDL RTL files, as well as an XDC constraints file.
The design used for Lab 4 is available as a Reference Design from the Xilinx website. See information in Locating Design Files for Lab 4.
The CPU Netlist and BFT Core designs target an XC7K70T device, and the design for Lab 4 targets an XCKU040 device. Running the tutorial with small designs allows for minimal hardware requirements and enables timely completion of the tutorial, as well as minimizing data size.