Now you will connect the interrupt signals on the various IP slaves to an interrupt controller through a Xilinx Concat block, to concatenate the individual interrupt signals into a bus. The Concat block is a general-purpose block to combine multiple inputs into a single bus output. The individual interrupt signals from different AXI slave cores need to be combined into a bus because the Interrupt Controller takes a bus at its input.
- Right-click the design canvas to open the popup menu and select Add IP.
- In the search field, type
concatto find the Xilinx Concat block, and double-click the core.
The Xilinx Concat core is instantiated onto the IP integrator design canvas, as shown in the following figure:
- Right-click the Concat block to open
the popup menu and select Customize
The Re-customize IP dialog box opens as shown in the following figure:
- For the Number of Ports field, enter
4, and click the mouse in the In0 Width field to accept the change.
The dialog box is updated to reflect the new number of input ports. Three ports are needed to connect the interrupt pins on the various slave IP blocks into the Interrupt Controller. You will use the fourth port to demonstrate tying a signal high or low with the Constant block.
- Click OK.
Now connect the interrupt signals of the AXI slaves to the Concat block to create an interrupt bus.Tip: To pull signals out of a bus, use the Slice block instead of the Concat block.
- Place the cursor on top of the
interruptpin of the AXI UART Lite.Note: The cursor changes into a pencil indicating that a connection can be made from that pin.
- Click and drag the cursor from the
interruptpin to an
inputpin on the Concat block.
As you drag the connection wire, a green checkmark appears on the Input port indicating that a valid connection can be made between these points.
- Release the mouse button and Vivado IP integrator makes a connection between the pins.
- Connect the interrupt pins on the AXI IIC block and the AXI Quad SPI block
to input pins on the Concat block, using the same process.
At this point, you have connected the interrupt signals to the Concat block, and there is a remaining unconnected input pin. You could re-customize the block to include only the required number of inputs. For this tutorial, you will use the Constant block to tie the extra input down instead.
- On the design canvas, right-click and select Add
The IP catalog opens.
- In the search field, type
consto find the Xilinx Constant block, and double-click the core in the IP catalog.
The Xilinx Constant block is instantiated into the subsystem design.
- Relocate the block as needed to be close to the Concat block.
- Click and drag the cursor from the output pin on the Constant block, and connect
it to the dangling fourth input pin on the Concat block.
As you drag the connection wire, a green checkmark appears on the input pin indicating that a valid connection can be made between these points.
- Release the mouse button and Vivado IP
integrator makes a connection between the pins.
Double-clicking any of the interrupt pins on the various AXI slaves shows that by default they are active-High, or triggered on the rising edge. In this case, you must use the Constant block to tie down the fourth input on the Concat block to prevent needless interrupt.
- Double-click the Constant block to
re-customize the IP.
The Re-customize IP dialog box opens.
- For the Const Val field, enter
0, as shown in the following figure, and click OK.
The fourth input of the Concat block is no longer floating. Now you can connect the concatenated interrupt signals from the Concat block to the Interrupt Controller.
- Click and drag the cursor from the output pin on the Concat block,
dout[3:0], and connect it to the
intr[0:0]pin of the Interrupt Controller block.
- Click the Regenerate Layout button
redraw the subsystem design.
The optimized layout of the design should now look similar to the following figure:
Note: The 1-bit bus width of the interrupt signal on the Interrupt Controller block does not match the 4-bit signal width from the Concat block. The Vivado tools correct this automatically during design validation.Tip: When you instantiate an Interrupt Controller block, the interrupt port by default is 1-bit. During design validation, parameter propagation passes the width of the output signal from the Concat block to the input signal of the Interrupt Controller, and the port width on the interrupt controller changes automatically.
- Right-click the interrupt pin of the
Interrupt Controller to open the popup menu, and select Make External.
This connects the interrupt output pin to an output port that is outside the IP subsystem design, to a processor for example.
All the interrupts on the Interrupt Controller have a priority that is determined based on the order of connection to the Concat block. Bit-0 of the interrupt bus has the highest priority.
When the interrupt port goes high, or active, the processor determines which slave is causing the interrupt. Multiple interrupts are handled according to their priority.
- Click the command from the main menu.