In this lab, you will learn about using the Power Optimization features in Vivado® for UltraScale+™ devices. The lab will take you through the steps for invoking Power Optimization after synthesizing the design. It will also guide you on how to use the power optimization report, make decisions and selectively turn off power optimization on signals, blocks, and hierarchies.
optimizations do not affect performance, and have little impact on area and compile
time. In the previous Lab, the default block RAM power optimization was disabled (Step 9 of Lab 2) by setting a NoBramPowerOpt directive to