Design Suite User Guide: Power Analysis and Optimization
(UG907) for more
information on the
There are no tool gated blocks in this design, but assume that this block RAM is in the critical path:
This step makes sure the tool does not gate this block RAM.
- In the Tcl Console,
type this command:
set_power_opt -exclude_cells [get_cells dut/Cascaded_bram/gen_dut.bram_top_cascade/bram_cas/mem_reg_bram_0]
This prevents the tool from gating this block RAM.
- From the Flow
Navigator choose Run
Implementation, which in turn reruns
- Click Save in the Save Project dialog box to save the
synthesized design and implemented design constraints before launching
Click OK on the Save Constraints dialog box to save the changes in constraints from the
- In the Implementation Completed dialog box, select Open Implemented Design and click OK.