UltraScale+ Tutorial Design Files - 2022.1 English

Vivado Design Suite Tutorial: Power Analysis and Optimization (UG997)

Document ID
Release Date
2022.1 English

You can find a separate UltraScale+ folder containing the UltraScale+ tutorial design files in the contents of the zip file.

The following table describes the contents of the UltraScale+™ tutorial design files:

Files Description
/src Contains the design HDL and testbench for the simulation.
/src/dut_fpga.v Top module for the design.








Other design blocks.
dut_fpga_zcu102.xdc Contains clocking and timing constraints for the design.
/src/testbench.v Testbench for simulating the design.