This message reports the average size in kilobytes transferred per read.
PCIe® transactions from accelerator to host should be larger than ~1-2 megabytes to ensure efficient PCIe bandwidth usage. Blocks smaller than this accumulate extra overhead for data transfers. Blocks larger than this should be transferred optimally.
As different accelerator cards might have different bandwidth requirements, Xilinx recommends running the https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/host/host_global_bandwidth example on your accelerator board.
If your algorithm is intended to work on smaller blocks of data, you should consider creating a wrapper which allows multiple datasets to be transferred together, reaching the ideal transfer sizes.