Kernel to DDR Connection - 2022.1 English

Vitis Guidance Messaging (UG1315)

Document ID
UG1315
Release Date
2022-10-19
Version
2022.1 English

Description

This rule informs indicates that the DDR memory connected to the kernel is not in the same or adjacent super logic regions.

Explanation

Kernel compute unit (CU) instance and DDR memory resource floorplanning are keys to meeting your design's quality of results for frequency and resources. Floorplanning involves explicitly allocating CUs (a kernel instance) to SLRs and mapping CUs to DDR memory resources. When floorplanning, consider both CU resource usage and DDR memory bandwidth requirements

The largest Xilinx® FPGAs are made up of multiple stacked silicon dies. Each stack is referred to as a SLR and has a fixed amount of resources and memory including DDR memory interfaces. You can use the actual kernel resource utilization values to help distribute CUs across SLRs to reduce congestion in any one SLR.

The less congestion in an SLR, the better the tools can map the design to the FPGA resources and meet your performance target.

For more information, refer to Optimizing the Performance in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).

Resolution

For better performance,Xilinx recommends using kernels to connect to DDR memory interfaces within the same SLR or a neighboring SLR.

For example. If the kernel is in SLR0, it should be connected to DDR memory in either SLR0 or SLR1.