PCIe® transfer of data from the FPGA is not optimized. This is flagged when the transfer rate from FPGA to host is less than 70% of the maximum possible write transfer bandwidth of PCIe.
XRT computes all the data transfer from the FPGA to PCIe over a period of time and calculates the PCIe read transfer.
There are several factors that can reduce the read transfer usage of PCIe:
- The host using small buffers.
- DDR contention from host reading data to DDR memory and kernel reading data to the same DDR memory.
- The host receiving several smaller transfers.
Xilinx recommends aggregating the data to be transferred in a single buffer and send it over PCIe® to DDR memory. PCIe® bandwidth is usually reasonable if the buffer size to be transferred is about 4 KB. Use multiple DDR memory banks to remove issues from the host and kernel writing to same the memory.