#--------------------- Setup estimation ---------------------
# Open example project with HDL source files and timing constraints
create_project project_1 $work_dir/project_1 -part xc7k70tfbg676-2 -force
set_property target_language VHDL [current_project]
instantiate_example_design -template xilinx.com:design:cpu_hdl:1.0
#----------------------- Run Synthesis then Power estimation -----------------
# Run Vivado Design Suite synthesis and automatically
launch_runs synth_1
wait_on_run synth_1
#open design
open_run synth_1
# Display tool default assumed operating conditions
report_operating_conditions -all
# Set specific device and environment operating conditions
set_operating_conditions -ambient 25
set_operating_conditions -voltage {vccint 1.0 vccaux 1.71}
# Generate verbose post-synthesis power report
report_power -verbose -file ex1_post-synthesis.pwr
#------------------------ Run Implementation then Power estimation -----------
launch_runs impl_1
wait_on_run impl_1
#open design
open_run impl_1
# Generate post-implementation verbose power report
report_power -file ex1_post-implementation.pwr
# Return operating conditions to default for device
reset_operating_conditions -ambient -voltage {vccint vccaux}