Vitis Integrated Design Environment
The Vitis™ integrated design environment (IDE) can be used to target system programming of Xilinx devices including, Versal devices. It supports development of single and multiple AI Engine kernel applications. The following features are available in the tool.
- An optimizing C/C++ compiler that compiles the kernels and graph code making all of the necessary connections, placements, and checks to ensure proper functioning on the device.
- A fast functional simulator that is useful in identifying errors in the design. This simulator is an ideal choice for testing, debugging, and verifying your AI Engine design because of the speed of iteration and the high level of data visibility it provides.
- A cycle approximate simulator which models the timing and resources of the AI Engine array while using transaction-level SystemC models for the NoC, and DDR memory. This allows for faster performance analysis of your AI Engine applications and accurate estimation of the AI Engine resource use, with cycle-approximate timing information.
- A powerful debugging environment that works in both simulation and hardware environments. Various views are available, such as variables view, disassembly view, memory view, register view, and pipeline view.
Vitis Command Line Tools
Command line tools are available to build, simulate, and generate output files and reports.
- The AI Engine compiler compiles kernels and graph code into ELF files that are run on the AI Engine processors.
- The AI Engine simulator and x86simulator are tools for cycle approximate simulation and functional simulation respectively.
- The cross compiler for Arm® Core is provided for PS code compilation.
- The Vitis compiler is the system compilation and linking tool for integrating whole system together.
- The Vitis Analyzer IDE is available for report viewing and analysis of the output files and reports generated by the command line tools.
The AI Engine Tools and Flows User Guide (UG1076) contains a wealth of information on the design flow and tools' usage.