You can independently reset each of the APU CPU core in the software.
The APU MPCore reset can be triggered by FPD, WDT, or a software register write; however, APU MPCore is reset without gracefully terminating requests to and from the APU. The intent is that you use the LPD in case of catastrophic failures in the FPD. The APU reset is primarily for software debug.
The Zynq UltraScale+ Device Technical Reference Manual (UG1085) describes the APU reset sequence.