External RTL Traffic Generator and AI Engine Simulation - 2022.2 English

The same technique can be deployed to drive traffic from the external System Verilog/Verilog traffic generators/test benches to the AI Engine simulator or x86-simulator.

Figure 1. XTLM Test Bench Hierarchy

To generate the AI Engine wrapper stub module (aie_wrapper_ext_tb.v) use the following steps:

1. The wrapper stubs will be generated based on the external PLIO declarations in the ADF graph. You need to perform the ADF graph compilation to generate scsim_config.json file that resides in ./Work/config/scsim_config.json directory. This config file contains information on the PLIOs declared in the graph. For more details on how to perform ADF graph compilation and external PLIOs declaration, refer to Versal ACAP AI Engine Programming Environment User Guide (UG1076).
2. Using this config file as argument to the gen_aie_wrapper.py script, you can auto-generate Verilog stub modules based on ext PLIO declared in ADF Graph:

   python3 ${XILINX_VITIS}/data/emulation/scripts/gen_aie_wrapper.py \
   -json Work/config/scsim_config.json --mode <wrapper/vivado> 

   Tip: The python script is available in the Vitis installation area as shown in the example above. There are two modes for the script: wrapper and Vivado mode. By default, the script runs in Vivado mode.

The name of the instance stubs must be identical to the name of the corresponding external PLIOs in the graph and will be reflected in the generated aie_wrapper_ext_tb.v file.

After running the gen_aie_wrapper.py script you can see aie_wrapper_ext_tb.v is generated that has instances of sim_ipc_axis modules that can be directly instantiated in your external test bench.