A typical hardware acceleration flow consists of identifying compute-intensive portions of applications or algorithms and implementing them as custom-designed hardware. These custom-designed hardware elements are typically called accelerators in domains such as heterogeneous computing; in Vitis™ nomenclature, they are also called kernels. Generally, these functions or kernels take significant execution time when run in pure software on x86 or Arm® -based host machines. With the Vitis acceleration flow, once a function or set of functions is chosen for acceleration, Vitis HLS or an RTL flow based on the Vivado Design Suite can be used to design or generate custom hardware. The host application can be written using XRT native APIs, or OpenCL™ C or C++ that links to the Xilinx Runtime (XRT).
The process of designing an accelerated application consists of choosing the compute-intensive functions for acceleration and designing custom hardware to accelerate these functions. Additionally, you must write software that runs on a host machine that orchestrates data movements to and from the accelerator. An important and tedious step in the overall application design consists of optimizing the data movements, especially over PCIe® or a network interface. These data movements consist of transfers between the host and kernel through global memories or network ports, and can be optimized based on the nature of the transfers. The accelerated hardware can also be composed of multiple functions, either as repeated functionality to process data in parallel or as a connected pipeline. Such compositions can consist of the same or different accelerated function instances, or it can be a mix of software and hardware functions.
Thus, the perfect system architecture is developed over an iterative design process. Essentially there are three design aspects being developed together: the kernel code, the supporting application or host code, and the hardware/software system interface and composition. While improving the overall design performance, changing one design aspect will invariably require changing another aspect. Vitis™ System Compilation mode (shortened as VSC) provides a single source unified C++ model that can make the design exploration process fast and easy. VSC is designed to be a framework to:
- Ease host side development by simplifying host code that controls the accelerated hardware
- Facilitate experimentation with compute unit replication to leverage data parallelism in the application
- Enable task-chaining composition on software and hardware side with multiple accelerated and software functions
- Serve the purpose of abstracting low-level hardware APIs, making it look like software programming
- Easily model concurrent or multi-threaded software code, and making it seamlessly integrate with end-user application code