Streaming Interfaces - 2022.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
Release Date
2022-12-07
Version
2022.2 English

The streaming interfaces page allows configuration of AXI4-Stream interfaces on the kernel. Streaming interfaces are only available on select platforms and if the chosen platform does not support streaming, then the page does not appear. Streaming interfaces are used for direct kernel-to-kernel communication as described in Streaming Data Transfers.

Figure 1. RTL Kernel Wizard Streaming Interfaces Page
Number of AXI4-Stream interfaces
Specifies the number of AXI4-Stream interfaces that exist on the kernel. A maximum of 32 interfaces can be enabled per kernel. Xilinx recommends keeping the number of interfaces as low as possible to reduce the amount of area consumed.
Name
Specifies the name of the interface. To ensure maximum compatibility, the argument name follows the same identifier rules as the kernel name.
Mode
Specifies whether the interface is a master or slave interface. An AXI4-Stream slave interface is a read-only interface, and an AXI4-Stream master interface is a write-only interface.
Width (bytes)
Specifies the TDATA width (in bytes) of the AXI4-Stream interface. This interface width is limited to 1 to 64 bytes in powers of 2.
Has TSTRB
Specifies the TSTRB signal of the AXI4-Stream interface is present on the kernel.
TUSER Width (bits)
Specifies the TUSER signal width (in bits) of the AXI4-Stream interface. This interface width is limited to 0 to 512 bits.
TID (bits)
Specifies the TID signal width (in bits) of the AXI4-Stream interface. This interface width is limited to 0 to 32 bits.
TDEST (bits)
Specifies the TDEST signal width (in bits) of the AXI4-Stream interface. This interface width is limited to 0 to 32 bits.

The streaming interface uses the TDATA/TKEEP/TLAST signals of the AXI4-Stream protocol. Stream transactions consists of a series of transfers where the final transfer is terminated with the assertion of the TLAST signal. Stream transfers must adhere to the following:

  • AXI4-Stream transfer occurs when TVALID/TREADY are both asserted.
  • TDATA must be 8, 16, 32, 64, 128, 256, or 512 bits wide.
  • TKEEP (per byte) must be all 1s when TLAST is 0.
  • TKEEP can be used to signal a ragged tail when TLAST is 1. For example, on a 4-byte interface, TKEEP can only be 0b0001, 0b0011, 0b0111, or 0b1111 to specify the last transfer is 1-byte, 2 bytes, 3 bytes, or 4 bytes in size, respectively.
  • TKEEP cannot be all zeros (even if TLAST is 1).
  • TLAST must be asserted at the end of a packet.
  • TREADY input/TVALID output should be low if kernel is not started to avoid lost transfers.