Terminology for Embedded System Design - 2022.2 English

The following introduces some of the tools and terms you will encounter in this document.

Vitis core development kit

Provides a framework for designing, building, and debugging heterogeneous applications using standard programming languages for both software and hardware components.

Vivado Design Suite

An RTL language design, synthesis, and implementation tool that enables hardware designers to create and export hardware designs (.xsa).

Xilinx Support Archive (.xsa)

Is a hardware container exported from the Vivado Design Suite for multiple uses, including in a fixed or extensible platform.

Fixed Platform (.xpfm)

Includes a completed hardware design (.xsa) and supporting software files defining the operating system, libraries, and boot files. In this context, "fixed" simply means that the hardware design is complete.

Extensible Platform (.xpfm)

The target platform of the Vitis heterogeneous system design flow. In this context, the "extensible" design can be further customized by adding programmable content such as PL kernels and AI Engine graph applications to the platform to build the embedded system. Extensible Platform can also be used to develop software like the fixed platform.

PL kernel (.xo)

A hardware function that can be added to the PL region of an extensible platform to define custom hardware. PL kernels can be defined using C++ code in Vitis HLS, or using RTL code and the IP packager feature of the Vivado Design Suite.

Vitis HLS

A high-level synthesis tool that translates C/C++ functions into RTL for implementation in the programmable logic (PL) region of a device. Vitis HLS generates a compiled object (.xo) file that can be imported into the Vitis environment.

Vitis Compiler

The v++ command used to compile PL kernels (.xo) from C++ code, and to link multiple PL kernels with hardware platforms and AI Engine graph applications to build the device binary.

PS Application

A user-defined software application to be run on an Arm processor in a Xilinx MPSoc or ACAP device, that can control and interact with PL kernels and AI Engine graph.

Xilinx runtime library (XRT)

Provides an API and drivers to let your software application control, transfer data to, and read the status of the PL kernels and AI Engine graph application in the hardware design.

AI Engine kernel and graph applications

Compiled by the Vitis aiecompiler and linked into the embedded system with v++. Kernels are functions that run on Versal AI Engines and form the fundamental building blocks of a data flow graph application. The AI Engine graph application is an adaptive dataflow graph with deterministic behavior.

aiecompiler/aiesimulator

Vitis tools for the compilation and simulation of AI Engine graph applications.

Device Binary (.xclbin) file

Contains the programmable device image (PDI) for Versal ACAP or the bitstream for Zynq MPSoC, and metadata needed to control the hardware design.