The Vitis™ System Compilation mode (shortened as VSC) lets you create a unified single-source C++ model that captures the system composition, containing both the hardware accelerator code and the host application code (based on C-Threads). For use only in Data Center acceleration projects, VSC creates a system structure that captures design intent specified in the C++ model and generates the necessary host code linking to Xilinx Runtime (XRT) to execute the design. The model incorporates a run time software layer that has many automation features for executing the accelerator hardware and managing data transfers. VSC uses Vitis compilation and linking tools to generate an FPGA bitstream and design-dependent object code, or software drivers, which can be linked with the rest of the application to create an executable.
VSC supports most Alveo Data Center accelerator cards with a list available at Supported Platforms and Startup Examples.
This section contains the following chapters: