This section provides a brief overview of the Vitis application development flow for RTL designers. An image of this flow is shown below.
- Application Compilation using G++
The host program is written in C/C++ using XRT native API, and compiled using a
g++compiler to create a host executable file to run on the x86 processor. The host program interacts with RTL kernels in the PL region on the FPGA to complete the accelerated application.
- PL Kernel Creation using Vivado Design Suite
The RTL design is developed and optimized for Xilinx FPGA devices using the Vivado tools. The steps for kernel development in the Vivado tools include:
- Edit RTL code to design the function
- Verify the RTL using behavioral simulation in Vivado simulator
- Verify the RTL synthesis, place and route, and timing
- Analyze performance by reviewing timing reports
- Repeat previous steps until performance goals are met
- Package the RTL IP as a kernel (.xo) for use in the Vitis flow
- PL Kernel Linking using Vitis Tools
Xilinx object (.xo) files are linked with the target hardware platform by the Vitis linker to create a device binary file (.xclbin) that is loaded for execution on the Alveo accelerator card.Tip: This step will call Vivado place and route to generate the bitstream as part of the .xclbin file.
To help define the architecture of the device binary a configuration file (design.cfg) can be created to specify how the kernels are connected to the global memory or to each other, or define how many instances of a kernel (or Compute Unit) should be built in the device binary to allow multiple functions to run in parallel. This configuration file is passed to the Vitis linker to generate the .xclbin.
- Running the Application
- Finally, when you run the application the host program loads the .xclbin file generated by Vitis Compiler. The host application always runs on the CPU, and the RTL kernel can be run in emulation mode on the x86, or load the .xclbin on the FPGA on the Alveo accelerator card.